1. Field of the Invention
The present invention relates to an input signal detecting circuit for detecting a differential signal. This Patent application is based on Japanese Patent application No. 2007-057315. The disclosure thereof is incorporated herein by reference.
2. Description of Related Art
In recent years, data transfer between computers has been changed from a parallel transfer to a serial transfer in which transfer speed is fast. A circuit for recognizing reception of a signal when the signal is transmitted and received (hereinafter, to be referred to as an input signal detecting circuit) is standardized in the physical layers in many interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect), SATA (Serial AT Attachment), and SAS (Serial Attached Small Computer System Interface). Also, each of the standards defines a value of the input signal amplitude. In order that such standardized circuits operate normally, it is important that an input signal has an amplitude within a range in the standard, independently of the use environment of the circuit.
One of the especially important factors in the environment under which a circuit is used is a temperature. Typically, in many cases, an interface unit uses an analog circuit, and an analog circuit uses a differential comparing circuit. Also, the differential comparing circuit uses elements such as transistors and resistors. The transistor has a transfer conductance [S] (hereinafter, to be referred to as gm), and a voltage amplification factor of the differential comparing circuit is determined based on a load resistance and gm. When the thickness of a gate oxide film of the transistor is represented as Tox, a dielectric constant of the gate oxide film is represented as εox, the vacuum dielectric constant is represented as εo, and a mobility of a carrier is represented as μ, a capacitance Cox of the gate oxide film is represented by the following equation (1).
                              C          ox                =                                            ɛ              ox                        ⁢                          ɛ              o                                            T            ox                                              (        1        )            
Also, when a product of the capacitance Cox of the gate oxide film and the carrier mobility μ is represented as β and a current flowing between the drain and the source in the transistor is represented as Ids, a gate width of the transistor is represented as W, and a gate length of the transistor is represented as L, the transfer conductance gm can be represented by the following equation (2).gm=√{square root over (2×β×Ids×W×L)}  (2)
With reference to the equation (2), the transfer conductance gm varies in accordance with the temperature because the product β and the current Ids are included. Such variation of gm dependent on temperature has influence on the output amplitude of the differential comparing circuit. That is, the output amplitude of the differential comparing circuit is increased or decreased on the basis of the temperature. The input signal detecting circuit to which the differential comparing circuit is applied has a temperature condition under which the input signal within the range of the standard cannot be detected.
One conventional example of the input signal detecting circuit is Japanese Patent Application Publication (JP-P2006-054742A: first conventional example). FIG. 1 shows the configuration of the input signal detecting circuit disclosed in the first conventional example. With reference to FIG. 1, the conventional input signal detecting circuit includes differential comparing circuits CMP7 and CMP8 and an exclusive OR EOR3. Hereinafter, an N-channel MOS (Metal Oxide Semiconductor) transistor and a P-channel MOS transistor are referred to as an NMOS transistor and a PMOS transistor, respectively. The differential comparing circuit CMP7 includes NMOS transistors Mn9 and Mn10 as a differential pair, resistors R9 and R10 serving as load resistances, and a constant current source Ib7. One end of the constant current source Ib7 is connected to the sources of the NMOS transistors Mn9 and Mn10, and one end of the resistor R9 is connected to the drain of the NMOS transistor Mn9, and one end of the resistor R10 is connected to the drain of the NMOS transistor Mn10. The other end of the resistor R9 and the other end of the resistor R10 are connected to a power supply voltage VDD. The other end of the constant current source Ib7 is grounded. The differential comparing circuit CMP8 includes NMOS transistors Mn11 and Mn12 as a differential pair, resistors R11 and R12 serving as load resistances, a resistor Rb1 to supply an offset voltage Voff1, and a constant current source Ib8. One end of the constant current source Ib8 is connected to the sources of the NMOS transistors Mn11 and Mn12, and one end of the resistor R11 is connected to the drain of the NMOS transistor Mn11, and one end of the resistor R12 is connected to the drain of the NMOS transistor Mn12. The other end of the resistor R11 and the other end of the resistor R12 are connected to one end of the resistor Rb1, and the other end of the resistor Rb1 is connected to the power supply voltage VDD. The other end of the constant current source Ib8 is grounded.
The gates of the NMOS transistors Mn9 and Mn11 are connected to an input terminal to which an input signal SINP is supplied, and the gates of the NMOS transistors Mn10 and Mn12 are connected to an input terminal to which an input signal SINN is supplied. The NMOS transistor Mn9 is connected to the resistor R9 through a node N9. The NMOS transistor Mn10 is connected to the resistor R10 through a node N10. The NMOS transistor Mn11 is connected to the resistor R11 through a node N11. The NMOS transistor Mn12 is connected to the resistor R12 through a node N12. A differential output signal CMP7out, which is composed of an output signal CMP7outP as a positive (normal) phase signal and an output signal CMP7outN as a negative (opposite) phase signal, is outputted from the nodes N9 and N10. A differential output signal CMP8out, which is composed of an output signal CMP8outP as a positive (normal) phase signal and an output signal CMP8outN as a negative (opposite) phase signal, is outputted from the nodes N11 and N12. The exclusive OR EOR3 is connected to the nodes N9 to N12 and outputs a signal of an exclusive OR result between the differential output signal CMP7out and the differential output signal CMP8out (an output signal Sout (binary signals Sout3P and Sout3N)).
FIGS. 2A, 2B and 2C are timing charts of the operation signals at nodes in the input signal detecting circuit according to the conventional example. With reference to FIG. 2A, a differential input signal SIN is composed of the input signal SINP as the positive phase signal, and the input signal SINN as the negative phase signal, and is supplied to the input signal detecting circuit. It is supposed that the detection of the differential input signal SIN is not required between a time t1 and a time t5, and the detection of the differential input signal SIN is required between the time t5 and a time t9. The input signal SINP is supplied to the NMOS transistors Mn9 and Mn11, and the input signal SINN is supplied to the NMOS transistors Mn10 and Mn12. When a load resistance of the differential comparing circuit is assumed to be RL and a voltage (amplitude) of the input signal to the differential comparing circuit is assumed to be Vin, a voltage (amplitude) Vo of the output signal from the differential comparing circuit is represented by the following equation (3).Vo=gm×RL×Vin  (3)Here, the voltages of the input signals SINP and SINN are assumed to be SINP and SINN, respectively, the voltages of the output signals CMP7outP, CMP7outN, CMP8outP and CMP8outN are assumed to be CMP7outP, CMP7outN, CMP8outP and CMP8outN, respectively, and the resistances of the resistors R9, R10, R11 and R12 as the load resistances are assumed to be R9, R10, R11 and R12, respectively. At this time, the equation (3) is represented by the following equations (4) and (5).CMP7outP−CMP7outN=rm×R9×(SINP−SINN)  (4)CMP8outP−CMP8outN=rm×R11×(SINP−SINN)  (5)Here, R9=R10 and R11=R12.
As shown by the equations (4) and (5), the input signal SIN (SINP−SINN) is amplified for the values of gm×R9 and gm×R11 as the voltage amplification factors of the differential comparing circuits CMP7 and CMP8 and is outputted as the differential output signals CMP7out (CMP7outP−CMP7outN) and CMP8out (CMP8outP−CMP8outN) of the differential comparing circuits CMP7 and CMP8 (refer to FIG. 2B).
DC operation voltages Vo7P and Vo7N of the output signals CMP7outP and CMP7outN of the differential comparing circuit CMP7 are determined from the following equations (6) and (7) by using the power supply voltage VDD, the resistors R9 and R10 and the constant current source Ib7 (a current value Ib7).
                                          V            o                    ⁢          7          ⁢          P                =                  VDD          -                                    R              ⁢                                                          ⁢              10              ×              Id              ⁢                                                          ⁢              7                        2                                              (        6        )                                                      V            o                    ⁢          7          ⁢          N                =                  VDD          -                                    R              ⁢                                                          ⁢              9              ×              Id              ⁢                                                          ⁢              7                        2                                              (        7        )            
On the other hand, DC operation voltages Vo8P and Vo8N of the output signals CMP8outP and CMP8outN of the differential comparing circuit CMP8 are calculated by using the power supply voltage VDD and the resistors Rb1 (the resistance value Rb1), R11 and R12. When the power supply voltage VDD, the resistors R9 and R10, R11 and R12, and the constant current sources Ib7 and Ib8 are the same power source, the same resistor and the same current source, the DC operation voltages Vo8P and Vo8N and the DC operation voltages Vo7P and Vo7N are separated by an offset voltage off1 indicated in the following equation (8).Voff1=Rb1×Ib8  (8)
Under this environment, the amplitude (SINP−SINN) of the differential input signal SIN is small between the time t1 and the time t5. As a result, the differential output signal CMP7out of the differential comparing circuit CMP7 and the differential output signal CMP8out of the differential comparing circuit CMP8 do not cross. On the other hand, since the amplitude of the differential input signal SIN is great between the time t5 and the time t9, the differential output signal CMP7out and the differential output signal CMP8out cross. The exclusive OR EOR3 compares the output signal CMP7outP and the output signal CMP8outN, and determines to be a logic level “1”, if the output signal CMP7outP is higher in voltage than the output signal CMP8outN, and determines to be a logic level “0” if the output signal CMP7outP is lower than the output signal CMP8outN. At the same time, the exclusive OR EOR3 compares the output signal CMP7outN and the output signal CMP8outP, and determines to be the logic level “1” if the output signal CMP8outP is higher in voltage than the output signal CMP7outN, and determines to be the logic level “0” if the output signal CMP8outP is lower in voltage than the output signal CMP7outN.
With reference to FIG. 2C, with the relation between the output signals Sout3P and Sout3N of the exclusive OR EOR3, when these two logic levels are all “1” or “0”, the output signal Sout3N is higher in voltage than the output signal Sout3P (a logic level “1”). On the contrary, when the two logic levels are different, the output signal Sout3N of the exclusive OR EOR3 is lower in voltage than the output signal Sout3P (a logic level “0”). In this way, when the differential input signal SIN having an amplitude to be detected is supplied, the logic level “0” is outputted as the output signal Sout. As mentioned above, the input signal detecting circuit according to the conventional examples can detect the differential input signal SIN so that the differential output signals CMP7out and CMP8out having amplitudes equal to or higher than the offset voltage Voff1 are obtained. That is, a threshold voltage (hereinafter, to be referred to as a detection threshold voltage) of the differential input signal SIN is set in accordance with the offset voltage Voff1 determined by the equation (8) such that the differential input signal SIN can be detected by the input signal detecting circuit according to the conventional example.
As shown in the equations (4) and (5), the amplitudes of the differential output signals CMP7out and CMP8out are determined in accordance with the transfer conductance gm whose value varies dependently on temperature. For this reason, even when the detectable differential input signal SIN, (having the amplitude equal to or higher than the detection threshold voltage is supplied, there would be a case that the differential output signals CMP7out and CMP8out having the correct amplitude cannot be outputted due to the influence of a peripheral temperature.
The equations (4) and (5) described in the operation of the above conventional circuit indicate a relation between the input and output of the differential comparing circuit. The voltage amplification factor of the typical voltage amplifying circuit is defined as (output voltage)/(input voltage)=voltage amplification factor=gm×RL, where RL is the load resistance. When this is applied to the differential comparing circuits CMP7 and CMP8 of the input signal detecting circuit according to the conventional example, the following equations (9) and (10) are obtained.
                                          (                                          CMP                ⁢                                                                  ⁢                7                ⁢                outP                            -                              CMP                ⁢                                                                  ⁢                7                ⁢                outN                                      )                                SINP            -            SINN                          =                  gm          ×          R          ⁢                                          ⁢          9                                    (        9        )                                                      (                                          CMP                ⁢                                                                  ⁢                8                ⁢                outP                            -                              CMP                ⁢                                                                  ⁢                8                ⁢                outN                                      )                                SINP            -            SINN                          =                  gm          ×          R          ⁢                                          ⁢          11                                    (        10        )            
As shown in the equation (2), the temperature variation in the transfer conductance gm results from the current flowing through the transistor and the product β of the capacitance Cox of the gate oxide film and the carrier mobility μ. In particular, a temperature variation amount of the transfer conductance gm dependent on the temperature variation in the carrier mobility μ is great, which causes a severe variation in the voltage amplification factor represented by the equations (9) and (10). On the other hand, when the offset voltage Voff1 is assumed to be stable for the temperature, the detection threshold voltage of the differential input signal SIN can be also assumed to be stable.
FIGS. 3A and 3B are diagrams showing the waveforms of the differential output signals 7out and 8out when the differential input signal SIN having an amplitude of the detection threshold voltage or more is supplied to the input signal detecting circuit according to the conventional example. FIGS. 3A and 3B show the waveforms when the peripheral temperature is −25° C. and 75° C. With reference to FIGS. 3A and 3B, even when the peripheral temperature varies from −25° C. to 75° C., the DC operation voltages Vo7P (Vo7N) and Vo8P (Vo8N) in the differential comparing circuits CMP7 and CM8 are 800 mV and 760 mV, respectively, and they does not almost vary. That is, the offset voltage is 40 mV, which is constant independently of the temperature. On the other hand, although the amplitudes of the differential output signals CMP7out and CMP8out are 50 mV at the temperature of −25° C., they decrease to 35 mV at the temperature of 75° C. In this case, the differential output signal 7out and the differential output signal 8out are separated by 5 mV, and the differential input signal SIN cannot be detected. In this way, there would be a case that the originally detectable input signal cannot be detected because the peripheral temperature increases.
Typically, the input signal detecting circuit for detecting a very small signal is strongly required to provide a high sensibility and simultaneously avoid erroneous detection. As a result, a detection voltage range, namely, an allowable range of the detection threshold voltage (the amplitude) becomes narrow. For this reason, it is necessary to reduce or remove detection irregularity caused based on peripheral temperature, as mentioned above.